RZ-G/RZ-G2 BSP Porting
RZ/G2 BSP Porting This page is to highlight important thing to consider when porting the Renesas BSP to your own custom board.
Add New DDR Settings
SoC: RZ/G2E, RZ/G2N, RZ/G2M, RZ/G2H
Flash Writer version v1.50+
- DDR settings for each board are stored in a "struct _boardcnf" that is used by the DDR initialization code.
- For Renesas evaluation boards, the Flash writer source contains an array of all the possible evaluation boards.
- When porting Flash Writer to your own custom board, you will need to create your own "struct _boardcnf" that matches the DDR memory on your board.
- In general, only the structure is needed (no DDR init executable code needs to be modified).
- In Flash Writer, the function boardcnf_get_brd_type() is declared as '__attribute__((weak))' such that you can provide your own version of this function and gcc will ignore the function provided in the Flash Writer code that is specific for Renesas evaluation boards. This method allows you to not modify source files that might be updated later by Renesas as new evaluation boards are added and might cause merge conflicts with your local modification.
- A sample DDR configuration structure has been provided. Please refer to file ddr/lpddr4/boot_init_dram_config-preset.c for example configurations used by Renesas evaluation boards.
1. Make a copy of the template file ddr/lpddr4/my_boot_dram_config.c
$ cp ddr/lpddr4/my_boot_dram_config.c ddr/lpddr4/xyz_boot_dram_config.c
2. Add your new file to the build system by editing the makefile ddr/lpddr4/ddr.mk
SRC_FILE += ddr/lpddr4/boot_init_dram.c ddr/lpddr4/boot_init_dram_config-preset.c # SRC_FILE += ddr/lpddr4/my_boot_dram_config.c SRC_FILE += ddr/lpddr4/xyz_boot_dram_config.c <<<<<<<<<<<< Example <<<<<<<<<<
3. Edit your new file and adjust the settings for your DDR memory on your board.
Add Support for New SPI Flash
- SoC: All
- Flash writer version: All
Flash Writer will read the device ID of the SPI flash device in order to determine what SPI commands it should use as well as the flash block size. Therefore, the specific ID of your flash device needs to be part of the flash writer source code.
The RZ/G2 Flash writer code is posted here.
Please review the following files and code and modify as needed.
- Confirm that the Manufacture ID for your flash devices is listed. For example, you will see these vendors already listed:
#define CYPRESS_MANUFACTURER_ID 0x01 /* Cypress */ #define WINBOND_MANUFACTURER_ID 0xEF /* Winbond */ #define MACRONIX_MANUFACTURER_ID 0xC2 /* Macronix */ #define MICRON_MANUFACTURER_ID 0x20 /* Micron */
- Confirm if the Device ID for your flash devices is listed. If not, then add it.
#define DEVICE_ID_S25FS128S 0x2018
- If you added a new SPI flash in dgmodule4.h, then you must add it to function CheckQspiFlashId()
- Add new case statement using your DEVICE_ID_xxx that you created in dgmodule.h
- Print out the part number of your SPI Flash using PutStr()
- Set the Flash sector erase size as gQspi_sa_size
- Set the address of the last Flash sector as gQspi_end_addess
case DEVICE_ID_S25FS512S: PutStr("S25FS512S", 1); gQspi_sa_size = SA_256KB; gQspi_end_addess = TOTAL_SIZE_64MB - 0x8000 - 1; break;
🎈 If you successfully added a new SPI Flash device, please let us know so we can update the code for everyone 🧑🤝🧑. You can submit a new issue on the github site, or send an email to email@example.com. Thank you.
Arm Trusted Firmware
[RZ/G2L] Quad SPI Flash Read Command Configuration
- After RESET, the internal Mask-ROM inside the device will read BL2 from SPI flash into internal memory. This process should work for almost all SPI flash devices and no code changes are needed.
- When BL2 runs, it will copy additional binaries into DDR (BL31, BL33, FIP, u-boot, etc..). However, the BL2 software will first reconfigure the SPI Flash controller to run in a memory mapped (XIP) mode in order to make the operation faster.
- Quad SPI flash devices from different vendors behave differently. Therefore, code changes will be needed. If the settings do not match your SPI flash, you will not boot.
- The file plat/renesas/rzg2l/drivers/io/rzg2l_io_memmap.c contains the function memmap_dev_open(). This function should be modified to match your SPI flash device.
- The arguments for function spi_multi_setup() should be modified to match your SPI flash device.
return spi_multi_setup(SPI_MULTI_ADDR_WIDES_24, SPI_MULTI_DQ_WIDES_1_4_4, SPI_MULTI_DUMMY_10CYCLE)
- You will define how to read data for the SPI flash. This means you are only concerned with the read commands in the SPI flash data sheet. You can decide if you want to use 1-bit access or 4-bit access.
- Options are defined in file plat/renesas/rzg2l/include/spi_multi.h
- SPI_MULTI_ADDR_WIDES_24: Use 24-bit (3 byte) addressing commands. Addressing is limited to 16MB
- SPI_MULTI_ADDR_WIDES_32: Use 32-bit (4 byte) addressing commands. Not all SPI flash supports these commands.
- SPI_MULTI_DQ_WIDES_1_1_1: Command is 1-bit, Address is 1-bit, Data is 1-bit. The FAST_READ command 0x0B(24-bit) or 0x0C(32-bit) is used.
- SPI_MULTI_DQ_WIDES_1_1_4: Command is 1-bit, Address is 4-bit, Data is 4-bit. The Quad Output FAST_READ command 0x6B(24-bit) or 0x6C(32-bit) is used
- SPI_MULTI_DQ_WIDES_1_4_4: Command is 1-bit, Address is 4-bit, Data is 4-bit. The Quad Input/Output FAST_READ command 0xEB(24-bit) or 0xEC(32-bit) is used
- SPI_MULTI_DUMMY_##CYCLE: Specify that ## number of 1-bit dummy cycles are added after the address is sent, but before data is read. These are hard requirements by the SPI flash vendor, and each vendor is different.
- The hex values for the SPI Flash Read commands for FAST_READ selected by SPI_MULTI_DQ_WIDES_x_x_x are defined in file "plat/renesas/rzg2l/include/spi_multi.h". If your SPI Flash uses a different hex value, you will need to make changes.
- We recommend that you start with this line below. It is the most simple and commonly supported on most SPI Flash devices.
/* Use FAST_READ command, only 1-bit for command, address and data. An 8-bit dummy cycle is inserted between address and reading data */ spi_multi_setup(SPI_MULTI_ADDR_WIDES_24, SPI_MULTI_DQ_WIDES_1_1_1, SPI_MULTI_DUMMY_8CYCLE);