RZ/G and RZ/V BSP Porting

This page is to highlight important things to consider when porting the Renesas BSP to your own custom board.

Overview

There is s a RZ/G2 Group Linux BSP Porting Guide document posted on Renesas.com.

• https://www.renesas.com/us/en/document/mas/rzg2-group-linux-bsp-porting-guide

This document contains information such as:

• How to add a new build configuration for a new board to a Yocto
• How to add a new build configuration for a new board to a u-boot
• Information about configuring pins and GPIO
• Information about Device Tree files for the kernel
• The code references are for the VLP64 v1.0.x releases *(the older Linux-4.19 BSP)
• The code refences are for the RZ/G2H,M,N,E devices.

One preliminary point to underline is that you may NOT want to use Yocto at the beginning, rather clone the repositories, modify the code and build it using a cross toolchain.

The paragraph order in this page is intentional. They represent the steps you normally do when you want to port the Renesas BSP, i.e. you absolutely want to start from Flash Writer. When you get your first custom board samples the non-volatile memories are virgin and the first goals is to program them with bootloaders. One of the first thing you need to do is to adjust the DDR configuration to your own. Debugging DDR may be tricky but have it working is a major step toward success. You can test the DDR using some hidden Flash Writer commands. After that you may need to change the SPI configuration.

Finally you can use Flash Writer to program the bootloaders: Arm Trusted Firmware (ATF) BL2 (aka IPL, Initial Program Loader), BL31 (Secure Monitor) and u-boot (BL33). BL32 is not strictly needed at the beginning, since it is the Trusted OS (optional). Bootloaders can be programmed into QSPI FLASH or eMMC, then of course the boot mode of the SoC shall be adjusted accordingly. ATF may also need to be configured depending on the non-volatile memory type. You may need to program separately (e.g. different files for each BL) or you can have a BL2 file and a FIP (Firmware Image Package) that includes all BL3x.

You do not normally need to modify many things in ATF and in any case only what is in the "plat/renesas/rz" folder. One of the first things ATF BL2 does is to configure the DDR. You would need to use the same (working) configuration used with Flash Writer, so there should be no surprise here, if the DDR works with Flash Writer then it will work with ATF as well.

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Then ATF loads BL31(image id=3), BL32 (again optionally, image id=4) and BL33 (u-boot, image id=5) from either QSPI or eMMC. Assuming everything goes fine u-boot prompt is finally reachable. The table below summarizes where the different actors in the boot process are typically stored and executed from.

Item	Stored into	Executed out of
Boot ROM	Internal SOC ROM	XIP (eXecuted In Place)
BL2	QSPI/eMMC boot part/SD card	Internal SRAM
BL31-BL32	QSPI/eMMC boot part/SD card	DDR (secured by TrustZone)
BL33 (u-boot)	QSPI/eMMC boot part/SD card	DDR
Linux kernel	eMMC/SD card	DDR
GNU OS (rootfs)	eMMC/SD card	DDR

The next step is to port the Linux CIP Kernel, by "porting" we mainly mean that the reference board device tree gets modified to reflect the HW available on the custom board.

Finally you can use Yocto to generate the root file system including all the bits and bobs you need to run your custom application.

Flash Writer

• RZ-G/RZ-G2_BSP_Porting_FlashWriter

Arm Trusted Firmware

• RZ-G/RZ-G2_BSP_Porting_ATF

u-boot

• RZ-G/RZ-G2_BSP_Porting_uboot

Linux Kernel

• RZ-G/RZ-G2_BSP_Porting_kernel

Yocto

• RZ-G/RZ-G2_BSP_Porting_Yocto

Ubuntu

• RZ-G/RZ-G2 BSP_Porting_Ubuntu

OpenWRT

• RZ-G/RZ-G2 BSP_Porting_OpenWRT

Debian

• RZ-G/RZ-G2 BSP Porting Debian

Memory Map

• This section explains how DDR Memory is divided and configured.
• RZ-G/RZ-G2_BSP_MemoryMap

Changing Console Port

You can make use of the following changes to change console port from SCIF0 to SCIF2 in RZ/G2L-LC and RZ/V2L (Not applicable for RZ/G2UL). Please note that it NOT RECOMMENDED by Renesas to do so and is described here only for experimental purpose.

• To redirect the output from SCIF0 to SCIF2, we need to change the stdout to reflect the respective console output in the ATF, u-boot and kernel. The output is obtained on PMOD1 through a UART module.
• We start by modifying the ATF:
  • The console driver is initialized with SCIF2 base address and the corresponding pin functions are defined enable the output through SCIF2.
  • The clock/reset signals are applied for SCIF2.
• Next we move onto u-boot where we redefine the stdout to to output on SCIF2 console.
• Finally in the kernel:
  • We once again redefine the stdout.
  • Enable the clock for SCIF2, so it is not put into standby mode.

RZ/G2L: Changing Console Port from SCIF0 to SCIF2

Trusted Firmware-A File: plat/renesas/rz/common/include/rzg2l_def.h #define RZG2L_SCIF0_BASE (0x1004B800) +#define RZG2L_SCIF2_BASE (0x1004C000) File: plat/renesas/rz/common/bl2_plat_setup.c initialize console driver */ ret = console_rzg2l_register( - RZG2L_SCIF0_BASE, + RZG2L_SCIF2_BASE, RZG2L_UART_INCK_HZ, RZG2L_UART_BARDRATE, &rzg2l_bl31_console); File: plat/renesas/rz/common/bl31_plat_setup.c initialize console driver */ ret = console_rzg2l_register( - RZG2L_SCIF0_BASE, + RZG2L_SCIF2_BASE, RZG2L_UART_INCK_HZ, RZG2L_UART_BARDRATE, &rzg2l_bl31_console); File: plat/renesas/rz/common/drivers/cpg.c { /* SCIF */ (uintptr_t)CPG_CLKON_SCIF, (uintptr_t)CPG_CLKMON_SCIF, - 0x001f0001, + 0x001f0004, CPG_T_CLK }, File: plat/renesas/rz/common/include/pfc_regs.h -#define PFC_MUX_TBL_NUM (4) +#define PFC_MUX_TBL_NUM (5) File: plat/renesas/rz/common/drivers/pfc.c { PFC_OFF, (uintptr_t)NULL, 0 } /* IEN */ +}, +/* P40(scif2) */ +{ + { PFC_ON, (uintptr_t)PFC_PMC40, 0x1F }, /* PMC */ + { PFC_ON, (uintptr_t)PFC_PFC40, 0x00011111 }, /* PFC */ + { PFC_OFF, (uintptr_t)PFC_IOLH40, 0x0000000101010101 }, /* IOLH */ + { PFC_OFF, (uintptr_t)PFC_PUPD40, 0x0000000000000000 }, /* PUPD */ + { PFC_OFF, (uintptr_t)PFC_SR40, 0x0000000101010101 }, /* SR */ + { PFC_OFF, (uintptr_t)NULL, 0 } /* IEN */ } #endif }; u-boot File: arch/arm/dts/smarc-rzg2l.dts aliases { serial0 = &scif0; + serial1 = &scif2; spi0 = &spibsc; }; chosen { - stdout-path = "serial0:115200n8"; + stdout-path = "serial1:115200n8"; }; kernel File: arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi /* comment the #define statement to disable SCIF2 (SER0) on PMOD1 (CN7) */ -//#define PMOD1_SER0 1 +#define PMOD1_SER0 1 File: arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi chosen { - stdout-path = "serial0:115200n8"; + stdout-path = "serial1:115200n8"; + bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; }; File: drivers/clk/renesas/r9a07g044-cpg.c static const unsigned int r9a07g044_crit_mod_clks[] __initconst = { MOD_CLK_BASE + R9A07G044_IA55_PCLK, MOD_CLK_BASE + R9A07G044_IA55_CLK, MOD_CLK_BASE + R9A07G044_DMAC_ACLK, + MOD_CLK_BASE + R9A07G044_SCIF2_CLK_PCK, };

Github Repositories

• These are the repositories where Renesas publishes the RZ code to.
  • https://github.com/renesas-rz/rz_linux-cip
  • https://github.com/renesas-rz/renesas-u-boot-cip
  • https://github.com/renesas-rz/rzg2_flash_writer
  • https://github.com/renesas-rz/rzg_trusted-firmware-a
• Information on each branch is located in the wiki section
  • https://github.com/renesas-rz/rz_linux-cip/wiki
  • https://github.com/renesas-rz/renesas-u-boot-cip/wiki
  • https://github.com/renesas-rz/rzg2_flash_writer/wiki
  • https://github.com/renesas-rz/rzg_trusted-firmware-a/wiki

How to build

The easiest and recommended way to build is by using these scripts. Otherwise you can install the toolchain as per these instructions and build manually following the instructions provided case by case.

Usually you also have to make sure that the path is correct and the triplet / quadruplet is set correctly, as well as the architecture. For example, a command similar to the following must be given before any make attempt:

PATH=/opt/arm/gcc-arm-10.2-2020.11-x86_64-aarch64-none-elf/bin:$PATH ; export CROSS_COMPILE=aarch64-none-elf-; export ARCH=arm64