RZ-Five/RZ-Five-BSP Porting

From Renesas.info

This page is to highlight important things to consider when porting the Renesas BSP to your own custom board.

The steps explained in this page are similar to what described for the Arm based devices (RZ/G2). To avoid duplications, the focus is on the differences, then you can refer to the RZ/G2 pages for anything common.


One preliminary point to underline, true also for Arm based devices, is that you may NOT want to use Yocto at the beginning, rather clone the repositories, modify the code and build it using a cross toolchain.

The toolchain itself is a point to discuss a bit more in depth, since RISC-V ecosystem is still not as mature as Arm's.

The paragraph order in this page is intentional. Similarly to what explained for Arm based device, they represent the steps you normally do when you want to port the Renesas BSP, i.e. you absolutely want to start from Flash Writer. When you get your first custom board samples the non-volatile memories are virgin and the first goals is to program them with bootloaders. One of the first thing you need to do is to adjust the DDR configuration to your own. Debugging DDR may be tricky but have it working is a major step toward success. You can test the DDR using some hidden Flash Writer commands. After that you may need to change the SPI configuration.

Then you can use Flash Writer to program the bootloaders: u-boot SPL (Secondary Program Loader), Open SBI (Supervisor Binary Interface and u-boot. Bootloaders can be programmed into QSPI FLASH or eMMC, then of course the boot mode of the SoC shall be adjusted accordingly. u-boot-spl may also need to be configured depending on the non-volatile memory type. Normally you do not need to program separately (e.g. different files for each boot loader), only two files, u-boot-spl and u-boot.itb, are needed but the Open SBI binary has to be included before building u-boot.

Some modifications may be needed in u-boot-spl. One of the first things spl does is to configure the DDR. You would need to use the same (working) configuration used with Flash Writer, so there should be no surprise here, if the DDR works with Flash Writer then it will work with ATF as well.

sci-usb boot.png-------------------------------

Then u-boot-spl loads Open SBI and u-boot, from either QSPI or eMMC. Assuming everything goes fine u-boot prompt is finally reachable.

The next step is to port the Linux CIP Kernel, by "porting" we mainly mean that the reference board device tree gets modified to reflect the HW available on the custom board.

Finally you can use Yocto to generate the root file system including all the bits and bobs you need to run your custom application.


The RISC-V toolchain is what is needed to cross-build everything, most likely it is going to be installed on a x86 machine and this is what is taken for granted in this section.

There are different toolchain that can be used:

  • Ubuntu 20.04 native apt package
  • Official RISC-V toolchain, to be build from sources
  • Andes customized toolchain, to be build from sources
  • SDK built using Yocto for RZ/Five

Ubuntu 20.04 native apt package

This option is very convenient for people using Ubuntu, the cross toolchain can be simply installed using apt:

sudo apt install gcc-riscv64-linux-gnu

Please note that in this case the cross gdb is not installed and in general the solution would be to install gdb-multiarch:

sudo apt-get install gdb-multiarch

However this multi-architecture gdb does not work perfectly with RZ/Five, so it is not recommended to use it.

Official RISC-V toolchain

Another option is to build the toolchain directly from the official RISC-V sources, available on github along with detailed instructions.

Andes customized toolchain

The core implemented in RZ/Five is an IP coming from Andes: AX45MP Single. Therefore their toolchain, also available on github, can be used successfully. It is enough to follow the instructions, making sure that the build script is edited to reflect the nds64le-elf-newlib-v5d or nds64le-linux-glibc-v5d settings. Note that these are not the default settings.

SDK for RZ/Five

The last possibility is to build the SDK using Yocto and install it on the host machine. Just follow the instructions available in the RZ/Five Board Support Package Release Note.

Flash Writer

Porting Flash Writer to RZ/Five is almost identical to RZ/G2L. Please refer to this page for more details. Of course some of the steps need to be adapted:

  • The branch to be selected is different:
git checkout origin/rz_five
  • param_mc.c should be copied in the ddr/five folder

u-boot-spl / u-boot

Porting u-boot to RZ/Five is similar to RZ/G2L. The major difference resides in SPL (Secondary Program Loader) that is enabled only in RZ/Five, since most of the time in Arm based devices the Arm Trusted Firmware BL2 performs all the low-level initialization needed.

Given the similarities, in this section only the differences are described. The github project to be cloned is the same (renesas-u-boot-cip), then the branch to be selected is different:

git checkout v20xx.xx/rzf-smarc

Replace the xx with the latest branch, or anyway the version you want to use.

Referring to the steps in this section, step 1 is slightly different:

1) Add you custom board device tree file in the arch/riscv/dts folder: my_custom_board.dts. You do not need to create this file from scratch, you can copy the Renesas board file as template:

cp arch/riscv/dts/smarc-rzf.dts arch/arm/dts/my_custom_board.dts

and edit the file arch/riscv/dts/Makefile:


dtb-$(CONFIG_TARGET_SMARC_RZF) += smarc-rzf.dtb
+dtb-$(CONFIG_TARGET_MY_CUSTOM_BOARD) += my_custom_board.dtb
targets += $(dtb-y)


Step 2 is almost identical, the only difference is that you want to start from a different board file:

mkdir -p board/<vendor>/my_custom_board
cp board/renesas/rzf-dev/* board/<vendor>/my_custom_board
mv board/<vendor>/my_custom_board/rzf-dev.c board/<vendor>/my_custom_board/my_custom_board.c

Step 3 is also very similar, edit the newly created files, board/<vendor>/my_custom_board/Kconfig:


config SYS_CPU
        default "rzfive"

config SYS_BOARD
        default "my_custom_board"

        default "vendor"

config SYS_SOC
        default "rzmpu"

        default "my_custom_board"


Open SBI

  • RZ-Five/RZ-Five BSP_Porting_SBI

Linux Kernel


Memory Map

  • This section explains how DDR Memory is divided and configured.
  • TBD

Github Repositories